The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
Continuous scaling of complementary metal-oxide-semiconductor (CMOS) devices requires borderless source/drain contact for self-aligned source/drain contact (SAC). When gate to gate pitch is extremely scaled, conventional source/drain contact technology faces gate-to-source/drain shorting issues. Borderless contacts have been used to prevent the shorting issues. To realize borderless contacts in replacement gate technology, a dielectric capping layer is typically formed on top of the gate so that the gate is isolated from the source/drain contact.
One method used to form the dielectric capping layer on top of the gate involves recessing the replacement gate electrode, typically metal consisting of work function metals, and aluminum, tungsten or silicon gap fill materials. Then, the recess is filled with dielectric material and the capping layer is deposited on top of the gate structure and polished. However, the recessing process is difficult to replicate uniformly across a plurality of gates on the wafer substrate during integrated circuit fabrication. The conventional etch process typically used in recessing is a landing process, i.e., it completely etches a selected material and stops when it reaches a different material. However, recessing the replacement gate electrode is not a landing process because recessing is not stopped at a different material. Rather, an upper portion of the fill material is removed until recessing is purposely stopped, leaving an underlying portion of the same fill material. Therefore, it is difficult to control within wafer (WIW) and water to wafer (WTW) uniformity to meet manufacturing standards. In fact, any integrated circuit fabrication process with direct etching without landing is extremely difficult to control in terms of etch rate, WIW variation, and WTW uniformity. Further, for aluminum, current etch processes may continue beyond the desired stopping point even after the process is stopped due to residual etching chemicals.
Accordingly, it is desirable to provide semiconductor device fabrication methods with enhanced control in recessing processes. In addition, it is desirable to provide semiconductor device fabrication methods that recess materials in repeatable increments on the order of an atomic layer. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.